Computerized devices control almost every aspect of our life—from writing documents to controlling traffic lights. However, computerized systems are bug-prone, and thus require a testing phase in which the bugs should be discovered. The testing phase is considered one of the most difficult tasks in designing a computerized device. The cost of not discovering a bug may be enormous, as the consequences of the bug may be disastrous. For example, a bug may cause the injury of a person relying on the designated behavior of the computerized system. Additionally, a bug in hardware or firmware of a marketed product may be expensive to fix, as patching it requires call-back of the computerized device. Hence, many developers of computerized systems invest a substantial portion of the development cycle in discovering erroneous behaviors of the computerized device.
When designing hardware projects, designer-level verification (DLV) is increasingly gaining acceptance as a necessary practice. As manufacturing processes are fast approaching physical limits, providers of high-end hardware systems look for highly optimized micro-architectures and unique functional features to differentiate their products. This trend puts a significant load on the size and complexity of the functional content provided by both the chip and system levels, and as a result drives a dramatic surge in the number of functional defects. The price and burden of correcting the bugs increase as the defects are identified closer to the product release. Hence, functional verification is becoming a prime factor in the hardware development process.
A straightforward method for reducing the cost of bugs is early identification and correction, by the developer of a logic block, prior to integration with other blocks. Unexpected behavior identified in the designer's environment, before releasing the code to integration, is simpler to analyze, has no impact on the integrated verification process, can be corrected without contributing to the logical-physical closure “churn”, and is therefore less likely to spawn new functional bugs. This is true for hardware as well as for software projects.
Designer-level verification for hardware projects is sometimes believed to not optimally utilize the designer's valuable expertise and time. However, discovering bugs at a later stage may require much more designer time as well as other resources, thus causing an enormous increase in the correction price.
Currently there are no efficient tools for hardware designers for testing their blocks prior to integration. Using verification-level tools requires specific knowledge of the complex tools and procedures, which may take a long time to master and use, since such tools are intended for use on large, integrated design units, and are therefore not adapted for the small component level of DLV.